#ifndef __UART_H__
#define __UART_H__

#include "main.h"

/* Register offsets */

#define UART_BASE_ADDR   (0xD0018000)

typedef struct UART_ {
	union
	{
		volatile uint32_t RBR;	 			// 0x0	Receive Buffer Register
		volatile uint32_t THR;	 			// 0x0	Transmit Holding Register
		volatile uint32_t DLL;	 			// 0x0	Divisor Latch (Low) (LCR[7] == 1)
	};
	union
	{
		volatile uint32_t IER;	 			// 0x4	Interrupt Enable Register
		volatile uint32_t DLH;	 			// 0x4	Divisor Latch (High) (LCR[7] == 1)
	};
	union
	{
		volatile uint32_t IIR;	 			// 0x8	Interrupt Identification Register
		volatile uint32_t FCR;	 			// 0x8	FIFO Control Register
	};
	volatile uint32_t LCR;	 				// 0xC	Line Control Register
	volatile uint32_t MCR;	 				// 0x10 Modem Control Register
	volatile uint32_t LSR;	 				// 0x14 Line Status Register
	volatile uint32_t MSR;	 				// 0x18 Modem Status Register
	volatile uint32_t SCR;	 				// 0x1C Scratchpad Register
	volatile uint32_t RSVD_0;	 			// 0x20 Reserved 0.
	volatile uint32_t RSVD_1;	 			// 0x24 Reserved 1.
	volatile uint32_t RSVD_2;	 			// 0x28 Reserved 2.
	volatile uint32_t RSVD_3;	 			// 0x2c Reserved 3.
	volatile uint32_t RSVD_4;	 			// 0x30 Reserved 4.
	volatile uint32_t RSVD_5;	 			// 0x34 Reserved 5.
	volatile uint32_t RSVD_6;	 			// 0x38 Reserved 6.
	volatile uint32_t RSVD_7;	 			// 0x3c Reserved 7.
	volatile uint32_t RSVD_8;	 			// 0x40 Reserved 8.
	volatile uint32_t RSVD_9;	 			// 0x44 Reserved 9.
	volatile uint32_t RSVD_10;	 			// 0x48 Reserved 10.
	volatile uint32_t RSVD_11;	 			// 0x4c Reserved 11.
	volatile uint32_t RSVD_12;	 			// 0x50 Reserved 12.
	volatile uint32_t RSVD_13;	 			// 0x54 Reserved 13.
	volatile uint32_t RSVD_14;	 			// 0x58 Reserved 14.
	volatile uint32_t RSVD_15;	 			// 0x5c Reserved 15.
	volatile uint32_t RSVD_16;	 			// 0x60 Reserved 16.
	volatile uint32_t RSVD_17;	 			// 0x64 Reserved 17.
	volatile uint32_t RSVD_18;	 			// 0x68 Reserved 18.
	volatile uint32_t RSVD_19;	 			// 0x6c Reserved 19.
	volatile uint32_t FAR;	 				// 0x70 FIFO Access Register
	volatile uint32_t TFR;	 				// 0x74 Transmit FIFO Read
	volatile uint32_t RFW;	 				// 0x78 Receive FIFO Write
	volatile uint32_t USR;	 				// 0x7C UART Status register
	volatile uint32_t RSVD_20;	 			// 0x80 Reserved 20.
	volatile uint32_t RSVD_21;	 			// 0x84 Reserved 21.
	volatile uint32_t RSVD_22;	 			// 0x88 Reserved 22.
	volatile uint32_t RSVD_23;	 			// 0x8c Reserved 23.
	volatile uint32_t RSVD_24;	 			// 0x90 Reserved 24.
	volatile uint32_t RSVD_25;	 			// 0x94 Reserved 25.
	volatile uint32_t RSVD_26;	 			// 0x98 Reserved 26.
	volatile uint32_t RSVD_27;	 			// 0x9c Reserved 27.
	volatile uint32_t RSVD_28;	 			// 0xa0 Reserved 28.
	volatile uint32_t HTX;	 				// 0xA4 Halt TX
	volatile uint32_t DMASA;	 			// 0xA8 DMA Software Acknowledge Register
	volatile uint32_t RSVD_29;	 			// 0xac Reserved 29.
	volatile uint32_t RSVD_30;	 			// 0xb0 Reserved 30.
	volatile uint32_t RSVD_31;	 			// 0xb4 Reserved 31.
	volatile uint32_t RSVD_32;	 			// 0xb8 Reserved 32.
	volatile uint32_t RSVD_33;	 			// 0xbc Reserved 33.
	volatile uint32_t DLF;	 				// 0xC0 Divisor Latch Fraction Register
	volatile uint32_t RSVD_34;	 			// 0xc4 Reserved 34.
	volatile uint32_t RSVD_35;	 			// 0xc8 Reserved 35.
	volatile uint32_t RSVD_36;	 			// 0xcc Reserved 36.
	volatile uint32_t UART_PROT_LEVEL;	 	// 0xD0 UART Protection level
	volatile uint32_t REG_TIMEOUT_RST;	 	// 0xD4 Register timeout counter reset value
} UART_t;

extern UART_t *const UART2;

/****************************** Bit definition for RBR register ********************************/

#define RBR_RBR_Pos		(0U)
#define RBR_RBR_Msk		(0xffUL << RBR_RBR_Pos)
#define RBR_RBR    		RBR_RBR_Msk


/****************************** Bit definition for IER register ********************************/

#define IER_ERBFI_Pos		(0U)
#define IER_ERBFI_Msk		(0x1UL << IER_ERBFI_Pos)
#define IER_ERBFI    		IER_ERBFI_Msk


#define IER_ETBEI_Pos		(1U)
#define IER_ETBEI_Msk		(0x1UL << IER_ETBEI_Pos)
#define IER_ETBEI    		IER_ETBEI_Msk


#define IER_ELSI_Pos		(2U)
#define IER_ELSI_Msk		(0x1UL << IER_ELSI_Pos)
#define IER_ELSI    		IER_ELSI_Msk


#define IER_EDSSI_Pos		(3U)
#define IER_EDSSI_Msk		(0x1UL << IER_EDSSI_Pos)
#define IER_EDSSI    		IER_EDSSI_Msk


#define IER_ELCOLR_Pos		(4U)
#define IER_ELCOLR_Msk		(0x1UL << IER_ELCOLR_Pos)
#define IER_ELCOLR    		IER_ELCOLR_Msk


#define IER_PTIME_Pos		(7U)
#define IER_PTIME_Msk		(0x1UL << IER_PTIME_Pos)
#define IER_PTIME    		IER_PTIME_Msk


/****************************** Bit definition for IIR register ********************************/

#define IIR_IID_Pos		(0U)
#define IIR_IID_Msk		(0xfUL << IIR_IID_Pos)
#define IIR_IID    		IIR_IID_Msk


#define IIR_FIFOSE_Pos		(6U)
#define IIR_FIFOSE_Msk		(0x3UL << IIR_FIFOSE_Pos)
#define IIR_FIFOSE    		IIR_FIFOSE_Msk


/****************************** Bit definition for LCR register ********************************/

#define LCR_DLS_Pos		(0U)
#define LCR_DLS_Msk		(0x3UL << LCR_DLS_Pos)
#define LCR_DLS    		LCR_DLS_Msk


#define LCR_STOP_Pos		(2U)
#define LCR_STOP_Msk		(0x1UL << LCR_STOP_Pos)
#define LCR_STOP    		LCR_STOP_Msk


#define LCR_PEN_Pos		(3U)
#define LCR_PEN_Msk		(0x1UL << LCR_PEN_Pos)
#define LCR_PEN    		LCR_PEN_Msk


#define LCR_EPS_Pos		(4U)
#define LCR_EPS_Msk		(0x1UL << LCR_EPS_Pos)
#define LCR_EPS    		LCR_EPS_Msk


#define LCR_SP_Pos		(5U)
#define LCR_SP_Msk		(0x1UL << LCR_SP_Pos)
#define LCR_SP    		LCR_SP_Msk


#define LCR_BC_Pos		(6U)
#define LCR_BC_Msk		(0x1UL << LCR_BC_Pos)
#define LCR_BC    		LCR_BC_Msk


#define LCR_DLAB_Pos		(7U)
#define LCR_DLAB_Msk		(0x1UL << LCR_DLAB_Pos)
#define LCR_DLAB    		LCR_DLAB_Msk


/****************************** Bit definition for MCR register ********************************/

#define MCR_DTR_Pos		(0U)
#define MCR_DTR_Msk		(0x1UL << MCR_DTR_Pos)
#define MCR_DTR    		MCR_DTR_Msk


#define MCR_RTS_Pos		(1U)
#define MCR_RTS_Msk		(0x1UL << MCR_RTS_Pos)
#define MCR_RTS    		MCR_RTS_Msk


#define MCR_OUT1_Pos		(2U)
#define MCR_OUT1_Msk		(0x1UL << MCR_OUT1_Pos)
#define MCR_OUT1    		MCR_OUT1_Msk


#define MCR_OUT2_Pos		(3U)
#define MCR_OUT2_Msk		(0x1UL << MCR_OUT2_Pos)
#define MCR_OUT2    		MCR_OUT2_Msk


#define MCR_LOOPBACK_Pos		(4U)
#define MCR_LOOPBACK_Msk		(0x1UL << MCR_LOOPBACK_Pos)
#define MCR_LOOPBACK    		MCR_LOOPBACK_Msk


#define MCR_AFCE_Pos		(5U)
#define MCR_AFCE_Msk		(0x1UL << MCR_AFCE_Pos)
#define MCR_AFCE    		MCR_AFCE_Msk


#define MCR_SIRE_Pos		(6U)
#define MCR_SIRE_Msk		(0x1UL << MCR_SIRE_Pos)
#define MCR_SIRE    		MCR_SIRE_Msk


/****************************** Bit definition for LSR register ********************************/

#define LSR_DR_Pos		(0U)
#define LSR_DR_Msk		(0x1UL << LSR_DR_Pos)
#define LSR_DR    		LSR_DR_Msk


#define LSR_OE_Pos		(1U)
#define LSR_OE_Msk		(0x1UL << LSR_OE_Pos)
#define LSR_OE    		LSR_OE_Msk


#define LSR_PE_Pos		(2U)
#define LSR_PE_Msk		(0x1UL << LSR_PE_Pos)
#define LSR_PE    		LSR_PE_Msk


#define LSR_FE_Pos		(3U)
#define LSR_FE_Msk		(0x1UL << LSR_FE_Pos)
#define LSR_FE    		LSR_FE_Msk


#define LSR_BI_Pos		(4U)
#define LSR_BI_Msk		(0x1UL << LSR_BI_Pos)
#define LSR_BI    		LSR_BI_Msk


#define LSR_THRE_Pos		(5U)
#define LSR_THRE_Msk		(0x1UL << LSR_THRE_Pos)
#define LSR_THRE    		LSR_THRE_Msk


#define LSR_TEMT_Pos		(6U)
#define LSR_TEMT_Msk		(0x1UL << LSR_TEMT_Pos)
#define LSR_TEMT    		LSR_TEMT_Msk


#define LSR_RFE_Pos		(7U)
#define LSR_RFE_Msk		(0x1UL << LSR_RFE_Pos)
#define LSR_RFE    		LSR_RFE_Msk


/****************************** Bit definition for MSR register ********************************/

#define MSR_DCTS_Pos		(0U)
#define MSR_DCTS_Msk		(0x1UL << MSR_DCTS_Pos)
#define MSR_DCTS    		MSR_DCTS_Msk


#define MSR_DDSR_Pos		(1U)
#define MSR_DDSR_Msk		(0x1UL << MSR_DDSR_Pos)
#define MSR_DDSR    		MSR_DDSR_Msk


#define MSR_TERI_Pos		(2U)
#define MSR_TERI_Msk		(0x1UL << MSR_TERI_Pos)
#define MSR_TERI    		MSR_TERI_Msk


#define MSR_DDCD_Pos		(3U)
#define MSR_DDCD_Msk		(0x1UL << MSR_DDCD_Pos)
#define MSR_DDCD    		MSR_DDCD_Msk


#define MSR_CTS_Pos		(4U)
#define MSR_CTS_Msk		(0x1UL << MSR_CTS_Pos)
#define MSR_CTS    		MSR_CTS_Msk


#define MSR_DSR_Pos		(5U)
#define MSR_DSR_Msk		(0x1UL << MSR_DSR_Pos)
#define MSR_DSR    		MSR_DSR_Msk


#define MSR_RI_Pos		(6U)
#define MSR_RI_Msk		(0x1UL << MSR_RI_Pos)
#define MSR_RI    		MSR_RI_Msk


#define MSR_DCD_Pos		(7U)
#define MSR_DCD_Msk		(0x1UL << MSR_DCD_Pos)
#define MSR_DCD    		MSR_DCD_Msk


/****************************** Bit definition for SCR register ********************************/

#define SCR_SCR_Pos		(0U)
#define SCR_SCR_Msk		(0xffUL << SCR_SCR_Pos)
#define SCR_SCR    		SCR_SCR_Msk


/****************************** Bit definition for FAR register ********************************/

#define FAR_FAR_Pos		(0U)
#define FAR_FAR_Msk		(0x1UL << FAR_FAR_Pos)
#define FAR_FAR    		FAR_FAR_Msk


/****************************** Bit definition for TFR register ********************************/

#define TFR_TFR_Pos		(0U)
#define TFR_TFR_Msk		(0xffUL << TFR_TFR_Pos)
#define TFR_TFR    		TFR_TFR_Msk


/****************************** Bit definition for RFW register ********************************/

#define RFW_RFWD_Pos		(0U)
#define RFW_RFWD_Msk		(0xffUL << RFW_RFWD_Pos)
#define RFW_RFWD    		RFW_RFWD_Msk


#define RFW_RFPE_Pos		(8U)
#define RFW_RFPE_Msk		(0x1UL << RFW_RFPE_Pos)
#define RFW_RFPE    		RFW_RFPE_Msk


#define RFW_RFFE_Pos		(9U)
#define RFW_RFFE_Msk		(0x1UL << RFW_RFFE_Pos)
#define RFW_RFFE    		RFW_RFFE_Msk


/****************************** Bit definition for USR register ********************************/

#define USR_BUSY_Pos		(0U)
#define USR_BUSY_Msk		(0x1UL << USR_BUSY_Pos)
#define USR_BUSY    		USR_BUSY_Msk


/****************************** Bit definition for HTX register ********************************/

#define HTX_HTX_Pos		(0U)
#define HTX_HTX_Msk		(0x1UL << HTX_HTX_Pos)
#define HTX_HTX    		HTX_HTX_Msk


/****************************** Bit definition for DMASA register ********************************/

#define DMASA_DMASA_Pos		(0U)
#define DMASA_DMASA_Msk		(0x1UL << DMASA_DMASA_Pos)
#define DMASA_DMASA    		DMASA_DMASA_Msk


/****************************** Bit definition for DLF register ********************************/

#define DLF_DLF_Pos		(0U)
#define DLF_DLF_Msk		(0x3fUL << DLF_DLF_Pos)
#define DLF_DLF    		DLF_DLF_Msk


/****************************** Bit definition for UART_PROT_LEVEL register ********************************/

#define UART_PROT_LEVEL_UART_PROT_LEVEL_Pos		(0U)
#define UART_PROT_LEVEL_UART_PROT_LEVEL_Msk		(0x7UL << UART_PROT_LEVEL_UART_PROT_LEVEL_Pos)
#define UART_PROT_LEVEL_UART_PROT_LEVEL    		UART_PROT_LEVEL_UART_PROT_LEVEL_Msk


/****************************** Bit definition for REG_TIMEOUT_RST register ********************************/

#define REG_TIMEOUT_RST_REG_TIMEOUT_RST_Pos		(0U)
#define REG_TIMEOUT_RST_REG_TIMEOUT_RST_Msk		(0xfUL << REG_TIMEOUT_RST_REG_TIMEOUT_RST_Pos)
#define REG_TIMEOUT_RST_REG_TIMEOUT_RST    		REG_TIMEOUT_RST_REG_TIMEOUT_RST_Msk


/****************************** Inline function for RBR register ********************************/

static inline void set_rbr_rbr(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RBR, RBR_RBR, VAL << RBR_RBR_Pos);
}

static inline uint32_t get_rbr_rbr(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RBR, RBR_RBR) >> RBR_RBR_Pos);
}

/****************************** Inline function for IER register ********************************/

static inline void set_ier_erbfi(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IER, IER_ERBFI, VAL << IER_ERBFI_Pos);
}

static inline uint32_t get_ier_erbfi(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IER, IER_ERBFI) >> IER_ERBFI_Pos);
}

static inline void set_ier_etbei(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IER, IER_ETBEI, VAL << IER_ETBEI_Pos);
}

static inline uint32_t get_ier_etbei(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IER, IER_ETBEI) >> IER_ETBEI_Pos);
}

static inline void set_ier_elsi(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IER, IER_ELSI, VAL << IER_ELSI_Pos);
}

static inline uint32_t get_ier_elsi(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IER, IER_ELSI) >> IER_ELSI_Pos);
}

static inline void set_ier_edssi(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IER, IER_EDSSI, VAL << IER_EDSSI_Pos);
}

static inline uint32_t get_ier_edssi(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IER, IER_EDSSI) >> IER_EDSSI_Pos);
}

static inline void set_ier_elcolr(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IER, IER_ELCOLR, VAL << IER_ELCOLR_Pos);
}

static inline uint32_t get_ier_elcolr(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IER, IER_ELCOLR) >> IER_ELCOLR_Pos);
}

static inline void set_ier_ptime(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IER, IER_PTIME, VAL << IER_PTIME_Pos);
}

static inline uint32_t get_ier_ptime(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IER, IER_PTIME) >> IER_PTIME_Pos);
}

/****************************** Inline function for IIR register ********************************/

static inline void set_iir_iid(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IIR, IIR_IID, VAL << IIR_IID_Pos);
}

static inline uint32_t get_iir_iid(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IIR, IIR_IID) >> IIR_IID_Pos);
}

static inline void set_iir_fifose(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->IIR, IIR_FIFOSE, VAL << IIR_FIFOSE_Pos);
}

static inline uint32_t get_iir_fifose(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->IIR, IIR_FIFOSE) >> IIR_FIFOSE_Pos);
}

/****************************** Inline function for LCR register ********************************/

static inline void set_lcr_dls(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LCR, LCR_DLS, VAL << LCR_DLS_Pos);
}

static inline uint32_t get_lcr_dls(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LCR, LCR_DLS) >> LCR_DLS_Pos);
}

static inline void set_lcr_stop(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LCR, LCR_STOP, VAL << LCR_STOP_Pos);
}

static inline uint32_t get_lcr_stop(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LCR, LCR_STOP) >> LCR_STOP_Pos);
}

static inline void set_lcr_pen(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LCR, LCR_PEN, VAL << LCR_PEN_Pos);
}

static inline uint32_t get_lcr_pen(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LCR, LCR_PEN) >> LCR_PEN_Pos);
}

static inline void set_lcr_eps(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LCR, LCR_EPS, VAL << LCR_EPS_Pos);
}

static inline uint32_t get_lcr_eps(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LCR, LCR_EPS) >> LCR_EPS_Pos);
}

static inline void set_lcr_sp(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LCR, LCR_SP, VAL << LCR_SP_Pos);
}

static inline uint32_t get_lcr_sp(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LCR, LCR_SP) >> LCR_SP_Pos);
}

static inline void set_lcr_bc(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LCR, LCR_BC, VAL << LCR_BC_Pos);
}

static inline uint32_t get_lcr_bc(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LCR, LCR_BC) >> LCR_BC_Pos);
}

static inline void set_lcr_dlab(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LCR, LCR_DLAB, VAL << LCR_DLAB_Pos);
}

static inline uint32_t get_lcr_dlab(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LCR, LCR_DLAB) >> LCR_DLAB_Pos);
}

/****************************** Inline function for MCR register ********************************/

static inline void set_mcr_dtr(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCR, MCR_DTR, VAL << MCR_DTR_Pos);
}

static inline uint32_t get_mcr_dtr(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCR, MCR_DTR) >> MCR_DTR_Pos);
}

static inline void set_mcr_rts(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCR, MCR_RTS, VAL << MCR_RTS_Pos);
}

static inline uint32_t get_mcr_rts(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCR, MCR_RTS) >> MCR_RTS_Pos);
}

static inline void set_mcr_out1(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCR, MCR_OUT1, VAL << MCR_OUT1_Pos);
}

static inline uint32_t get_mcr_out1(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCR, MCR_OUT1) >> MCR_OUT1_Pos);
}

static inline void set_mcr_out2(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCR, MCR_OUT2, VAL << MCR_OUT2_Pos);
}

static inline uint32_t get_mcr_out2(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCR, MCR_OUT2) >> MCR_OUT2_Pos);
}

static inline void set_mcr_loopback(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCR, MCR_LOOPBACK, VAL << MCR_LOOPBACK_Pos);
}

static inline uint32_t get_mcr_loopback(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCR, MCR_LOOPBACK) >> MCR_LOOPBACK_Pos);
}

static inline void set_mcr_afce(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCR, MCR_AFCE, VAL << MCR_AFCE_Pos);
}

static inline uint32_t get_mcr_afce(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCR, MCR_AFCE) >> MCR_AFCE_Pos);
}

static inline void set_mcr_sire(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MCR, MCR_SIRE, VAL << MCR_SIRE_Pos);
}

static inline uint32_t get_mcr_sire(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MCR, MCR_SIRE) >> MCR_SIRE_Pos);
}

/****************************** Inline function for LSR register ********************************/

static inline void set_lsr_dr(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LSR, LSR_DR, VAL << LSR_DR_Pos);
}

static inline uint32_t get_lsr_dr(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LSR, LSR_DR) >> LSR_DR_Pos);
}

static inline void set_lsr_oe(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LSR, LSR_OE, VAL << LSR_OE_Pos);
}

static inline uint32_t get_lsr_oe(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LSR, LSR_OE) >> LSR_OE_Pos);
}

static inline void set_lsr_pe(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LSR, LSR_PE, VAL << LSR_PE_Pos);
}

static inline uint32_t get_lsr_pe(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LSR, LSR_PE) >> LSR_PE_Pos);
}

static inline void set_lsr_fe(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LSR, LSR_FE, VAL << LSR_FE_Pos);
}

static inline uint32_t get_lsr_fe(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LSR, LSR_FE) >> LSR_FE_Pos);
}

static inline void set_lsr_bi(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LSR, LSR_BI, VAL << LSR_BI_Pos);
}

static inline uint32_t get_lsr_bi(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LSR, LSR_BI) >> LSR_BI_Pos);
}

static inline void set_lsr_thre(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LSR, LSR_THRE, VAL << LSR_THRE_Pos);
}

static inline uint32_t get_lsr_thre(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LSR, LSR_THRE) >> LSR_THRE_Pos);
}

static inline void set_lsr_temt(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LSR, LSR_TEMT, VAL << LSR_TEMT_Pos);
}

static inline uint32_t get_lsr_temt(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LSR, LSR_TEMT) >> LSR_TEMT_Pos);
}

static inline void set_lsr_rfe(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->LSR, LSR_RFE, VAL << LSR_RFE_Pos);
}

static inline uint32_t get_lsr_rfe(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->LSR, LSR_RFE) >> LSR_RFE_Pos);
}

/****************************** Inline function for MSR register ********************************/

static inline void set_msr_dcts(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSR, MSR_DCTS, VAL << MSR_DCTS_Pos);
}

static inline uint32_t get_msr_dcts(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSR, MSR_DCTS) >> MSR_DCTS_Pos);
}

static inline void set_msr_ddsr(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSR, MSR_DDSR, VAL << MSR_DDSR_Pos);
}

static inline uint32_t get_msr_ddsr(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSR, MSR_DDSR) >> MSR_DDSR_Pos);
}

static inline void set_msr_teri(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSR, MSR_TERI, VAL << MSR_TERI_Pos);
}

static inline uint32_t get_msr_teri(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSR, MSR_TERI) >> MSR_TERI_Pos);
}

static inline void set_msr_ddcd(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSR, MSR_DDCD, VAL << MSR_DDCD_Pos);
}

static inline uint32_t get_msr_ddcd(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSR, MSR_DDCD) >> MSR_DDCD_Pos);
}

static inline void set_msr_cts(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSR, MSR_CTS, VAL << MSR_CTS_Pos);
}

static inline uint32_t get_msr_cts(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSR, MSR_CTS) >> MSR_CTS_Pos);
}

static inline void set_msr_dsr(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSR, MSR_DSR, VAL << MSR_DSR_Pos);
}

static inline uint32_t get_msr_dsr(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSR, MSR_DSR) >> MSR_DSR_Pos);
}

static inline void set_msr_ri(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSR, MSR_RI, VAL << MSR_RI_Pos);
}

static inline uint32_t get_msr_ri(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSR, MSR_RI) >> MSR_RI_Pos);
}

static inline void set_msr_dcd(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->MSR, MSR_DCD, VAL << MSR_DCD_Pos);
}

static inline uint32_t get_msr_dcd(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->MSR, MSR_DCD) >> MSR_DCD_Pos);
}

/****************************** Inline function for SCR register ********************************/

static inline void set_scr_scr(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->SCR, SCR_SCR, VAL << SCR_SCR_Pos);
}

static inline uint32_t get_scr_scr(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->SCR, SCR_SCR) >> SCR_SCR_Pos);
}

/****************************** Inline function for FAR register ********************************/

static inline void set_far_far(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->FAR, FAR_FAR, VAL << FAR_FAR_Pos);
}

static inline uint32_t get_far_far(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->FAR, FAR_FAR) >> FAR_FAR_Pos);
}

/****************************** Inline function for TFR register ********************************/

static inline void set_tfr_tfr(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->TFR, TFR_TFR, VAL << TFR_TFR_Pos);
}

static inline uint32_t get_tfr_tfr(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->TFR, TFR_TFR) >> TFR_TFR_Pos);
}

/****************************** Inline function for RFW register ********************************/

static inline void set_rfw_rfwd(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFW, RFW_RFWD, VAL << RFW_RFWD_Pos);
}

static inline uint32_t get_rfw_rfwd(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFW, RFW_RFWD) >> RFW_RFWD_Pos);
}

static inline void set_rfw_rfpe(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFW, RFW_RFPE, VAL << RFW_RFPE_Pos);
}

static inline uint32_t get_rfw_rfpe(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFW, RFW_RFPE) >> RFW_RFPE_Pos);
}

static inline void set_rfw_rffe(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->RFW, RFW_RFFE, VAL << RFW_RFFE_Pos);
}

static inline uint32_t get_rfw_rffe(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->RFW, RFW_RFFE) >> RFW_RFFE_Pos);
}

/****************************** Inline function for USR register ********************************/

static inline void set_usr_busy(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->USR, USR_BUSY, VAL << USR_BUSY_Pos);
}

static inline uint32_t get_usr_busy(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->USR, USR_BUSY) >> USR_BUSY_Pos);
}

/****************************** Inline function for HTX register ********************************/

static inline void set_htx_htx(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->HTX, HTX_HTX, VAL << HTX_HTX_Pos);
}

static inline uint32_t get_htx_htx(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->HTX, HTX_HTX) >> HTX_HTX_Pos);
}

/****************************** Inline function for DMASA register ********************************/

static inline void set_dmasa_dmasa(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DMASA, DMASA_DMASA, VAL << DMASA_DMASA_Pos);
}

static inline uint32_t get_dmasa_dmasa(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DMASA, DMASA_DMASA) >> DMASA_DMASA_Pos);
}

/****************************** Inline function for DLF register ********************************/

static inline void set_dlf_dlf(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->DLF, DLF_DLF, VAL << DLF_DLF_Pos);
}

static inline uint32_t get_dlf_dlf(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->DLF, DLF_DLF) >> DLF_DLF_Pos);
}

/****************************** Inline function for UART_PROT_LEVEL register ********************************/

static inline void set_uart_prot_level_uart_prot_level(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->UART_PROT_LEVEL, UART_PROT_LEVEL_UART_PROT_LEVEL, VAL << UART_PROT_LEVEL_UART_PROT_LEVEL_Pos);
}

static inline uint32_t get_uart_prot_level_uart_prot_level(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->UART_PROT_LEVEL, UART_PROT_LEVEL_UART_PROT_LEVEL) >> UART_PROT_LEVEL_UART_PROT_LEVEL_Pos);
}

/****************************** Inline function for REG_TIMEOUT_RST register ********************************/

static inline void set_reg_timeout_rst_reg_timeout_rst(UART_t *INST, uint32_t VAL)
{
	MODIFY_REG(INST->REG_TIMEOUT_RST, REG_TIMEOUT_RST_REG_TIMEOUT_RST, VAL << REG_TIMEOUT_RST_REG_TIMEOUT_RST_Pos);
}

static inline uint32_t get_reg_timeout_rst_reg_timeout_rst(UART_t *INST)
{
	return (uint32_t)(READ_BIT(INST->REG_TIMEOUT_RST, REG_TIMEOUT_RST_REG_TIMEOUT_RST) >> REG_TIMEOUT_RST_REG_TIMEOUT_RST_Pos);
}

void set_boudrate();
void uart_init();

#endif // __UART_H__
